What are chiplets and why is the industry moving to them?

Chiplets are smaller dies made separately and assembled into a single package instead of building one large monolithic chip. They improve manufacturing yield, since a defect only ruins a small chiplet, and let designers mix process nodes to optimize cost. Modern high-end accelerators like NVIDIA's Blackwell and AMD's Instinct use this approach, and standards such as UCIe aim to let chiplets from different vendors work together.

What is high-bandwidth memory and why does it matter for AI?

High-bandwidth memory (HBM) is DRAM stacked vertically and connected to the processor through a very wide interface on a silicon interposer, delivering terabytes per second of bandwidth. It matters because large language model performance is frequently limited by how fast weights can be moved to the compute units, not by raw compute. Because HBM is hard to manufacture and supplied by only a few vendors, it has become a key bottleneck and cost driver for AI accelerators.

What is the difference between a GPU, a TPU, and an NPU?

A GPU is a general-purpose parallel processor originally built for graphics that also excels at the matrix math in AI, with NVIDIA's data-center GPUs being the market standard. A TPU is Google's custom ASIC built specifically for tensor operations, tightly integrated with its own software and interconnect. An NPU is a small, power-efficient accelerator embedded in a system-on-chip to run inference locally on phones, laptops, and edge devices.

Is RISC-V used in AI hardware?

Yes. RISC-V is an open, royalty-free instruction set that designers can extend with custom instructions, which makes it attractive for building AI accelerators and their control processors. Companies such as Tenstorrent build chips around RISC-V cores, and its vector extension provides a scalable path to data-parallel compute. Its openness also appeals to organizations wary of proprietary-ISA licensing and export restrictions.

How to Run LLMs on an NPU in Your Laptop

This is a practical, up-to-date guide to Run LLMs — what it is, why it matters in 2026, and how to apply it in real projects. It is written for developers and founders who want clear answers and proven best practices, not filler.

Whether you're just starting out or leveling up, treat this as a working reference you can return to. Every section is built to be skimmed, applied, and shared.

What Is an AI Accelerator?

An AI accelerator is specialized hardware designed to run the linear-algebra-heavy workloads of modern machine learning far more efficiently than a general-purpose CPU. The core operation these chips optimize is dense and sparse matrix multiplication, which dominates both the forward and backward passes of neural networks. Rather than a handful of powerful sequential cores, accelerators pack thousands of simpler arithmetic units alongside wide, fast memory to keep them fed. The category spans data-center GPUs like NVIDIA's H100, Google's TPUs, dedicated inference ASICs, on-device NPUs, and more experimental designs such as neuromorphic and photonic chips. What unites them is a shift from flexibility toward throughput per watt on a narrow but economically enormous class of tensor operations.

Neuromorphic Computing

Neuromorphic computing takes design cues from the brain, using spiking neural networks where information is carried by discrete events (spikes) rather than continuous dense arithmetic. Chips like Intel's Loihi 2 and IBM's TrueNorth and NorthPole colocate memory and computation and process events only when they occur, which can make them extremely energy-efficient for sparse, event-driven workloads. This event-based model suits applications such as always-on sensing, gesture recognition, and certain robotics and optimization problems. The catch is that mainstream deep learning is built around dense tensor math and standard training pipelines, so neuromorphic hardware requires different algorithms and lacks a mature software ecosystem. It remains largely a research and specialized-deployment technology rather than a general-purpose replacement for GPUs.

NPUs and On-Device Inference

A Neural Processing Unit is a compact accelerator integrated into a system-on-chip to run inference locally on phones, laptops, and embedded devices. Apple's Neural Engine, Qualcomm's Hexagon NPU, and the NPUs in Intel Core Ultra and AMD Ryzen AI processors all target the same goal: run models within a few watts and without a round trip to the cloud. This matters for latency-sensitive features, offline capability, and privacy, since data never leaves the device. NPU performance is often quoted in TOPS (trillions of operations per second) at low precision, and the recent Copilot+ PC category set an informal bar around 40 TOPS for on-device AI. The tradeoff is a tight power and memory envelope, so on-device models are heavily quantized and pruned.

Inference Chips Versus Training Chips

Training and inference stress hardware in different ways, and increasingly they use different chips. Training must store activations and gradients for backpropagation, favors high-precision-friendly formats, and benefits enormously from massive clusters with fast interconnects. Inference, by contrast, runs the model forward only, is dominated by latency and cost per token, and rewards high memory bandwidth to stream weights quickly. Startups like Groq, Cerebras, and SambaNova, along with Amazon's Inferentia, target inference specifically, sometimes trading flexibility for dramatically lower latency or better tokens-per-dollar. As deployed AI shifts from research toward serving billions of requests, the economic center of gravity is moving toward inference-optimized silicon.

Photonic Computing

Photonic computing performs computation using light rather than electrical currents, exploiting the physics of optics to do certain operations, especially matrix multiplication, with potentially very low energy and latency. Because light can carry many signals in parallel across different wavelengths and does not dissipate energy the way charging and discharging transistors does, photonics is attractive for the linear-algebra core of neural networks. Companies such as Lightmatter and Lightelligence are building photonic accelerators and, notably, optical interconnects that move data between chips using light. In fact, photonics is arriving first as interconnect, since co-packaged optics can relieve the communication bottleneck in large clusters. Pure photonic compute still faces challenges around analog precision, data conversion overhead, and integration, keeping it earlier-stage than the interconnect use case.

RISC-V in AI Hardware

RISC-V is an open, royalty-free instruction set architecture that has become a popular foundation for custom chips, including AI accelerators. Its appeal is extensibility: designers can add custom instructions for tensor or vector operations without licensing fees or permission from a gatekeeper, which is difficult with proprietary ISAs like x86 or Arm. In AI systems RISC-V frequently serves as the control processor that orchestrates dedicated matrix engines, and companies such as Tenstorrent build accelerators around RISC-V cores. The RISC-V Vector extension provides a scalable path to data-parallel compute. Geopolitical factors have further boosted interest, since an open ISA is harder to restrict through export controls than a single vendor's proprietary technology.

Run LLMs: Key Facts and Data

According to recent industry research and the official documentation linked below:

The Hopper-based H100 SXM offers 80 GB of HBM3 memory delivering roughly 3.35 TB/s of bandwidth, while the Blackwell B200 pairs two reticle-limited dies into one package with 192 GB of HBM3e and around 8 TB/s of bandwidth.
Training a frontier large language model can require tens of thousands of accelerators running for weeks; multiple industry reports place the hardware and compute cost of leading models in the tens to hundreds of millions of dollars.
Blackwell introduces native support for the FP4 (4-bit floating point) data format, which vendors report can roughly double inference throughput versus FP8 on comparable hardware for suitable models.

Quick-Reference Summary

A map of what this guide covers:

Topic	What you'll learn
What Is an AI Accelerator?	An AI accelerator is specialized hardware designed to run the linear-algebra-heavy workloads of modern machine learning far more efficiently than a general-purpose CPU.
Neuromorphic Computing	Neuromorphic computing takes design cues from the brain
NPUs and On-Device Inference	A Neural Processing Unit is a compact accelerator integrated into a system-on-chip to run inference locally on phones
Inference Chips Versus Training Chips	Training and inference stress hardware in different ways, and increasingly they use different chips.
Photonic Computing	Photonic computing performs computation using light rather than electrical currents
RISC-V in AI Hardware	RISC-V is an open, royalty-free instruction set architecture that has become a popular foundation for custom chips

How to Get Started with Run LLMs

A simple path that works:

Learn the fundamentals of Run LLMs from primary sources, not just tutorials.
Build one small, real project end to end.
Get feedback, refactor, and add tests.
Ship it publicly and document what you learned.
Repeat with a slightly harder project each time.

Build It with a World-Class Full Stack Developer

Sandeep Kumar Chaudhary is a full stack world-class developer. If you want to turn this into a real, production-ready product, get in touch — message directly on WhatsApp at +9779802348957 for a fast, no-pressure consult.

You can also explore the projects already shipped to thousands of users, or start a conversation here.

Final Thoughts

Match the chip to the phase: training rewards huge interconnected clusters, while inference rewards low latency, high memory bandwidth, and cheaper per-token economics. The developers and teams who win in 2026 pair strong fundamentals with consistent shipping. Start small, stay curious, build in public, and revisit this guide as your skills grow.