What Is Compute-in-Memory and How Do Analog MACs Work?
TL;DR
A complete, up-to-date breakdown of compute in memory for developers and founders. It covers the core ideas, the trade-offs that matter, a practical workflow, real numbers, and the questions people ask most — written to be skimmed, applied, and shared.
Key takeaways
- For on-device and edge AI, look at NPUs in the SoC (Apple, Qualcomm, Intel, AMD) rather than discrete GPUs to hit power and latency budgets.
- RISC-V is a credible base ISA for custom accelerators and control cores because it is open, royalty-free, and extensible with custom instructions.
- CUDA remains NVIDIA's deepest moat; budget real engineering time if you plan to port to AMD ROCm, Google TPUs, or custom silicon.
- Neuromorphic and photonic computing are promising but still mostly research-stage; treat them as long-horizon bets, not 2026 production defaults.
- Memory bandwidth, not raw FLOPS, is usually the real constraint for LLM inference, so read the HBM capacity and bandwidth spec before the TFLOPS number.
This is a practical, up-to-date guide to Compute in Memory — what it is, why it matters in 2026, and how to apply it in real projects. It is written for developers and founders who want clear answers and proven best practices, not filler.
Whether you're just starting out or leveling up, treat this as a working reference you can return to. Every section is built to be skimmed, applied, and shared.
Photonic Computing
Photonic computing performs computation using light rather than electrical currents, exploiting the physics of optics to do certain operations, especially matrix multiplication, with potentially very low energy and latency. Because light can carry many signals in parallel across different wavelengths and does not dissipate energy the way charging and discharging transistors does, photonics is attractive for the linear-algebra core of neural networks. Companies such as Lightmatter and Lightelligence are building photonic accelerators and, notably, optical interconnects that move data between chips using light. In fact, photonics is arriving first as interconnect, since co-packaged optics can relieve the communication bottleneck in large clusters. Pure photonic compute still faces challenges around analog precision, data conversion overhead, and integration, keeping it earlier-stage than the interconnect use case.
RISC-V in AI Hardware
RISC-V is an open, royalty-free instruction set architecture that has become a popular foundation for custom chips, including AI accelerators. Its appeal is extensibility: designers can add custom instructions for tensor or vector operations without licensing fees or permission from a gatekeeper, which is difficult with proprietary ISAs like x86 or Arm. In AI systems RISC-V frequently serves as the control processor that orchestrates dedicated matrix engines, and companies such as Tenstorrent build accelerators around RISC-V cores. The RISC-V Vector extension provides a scalable path to data-parallel compute. Geopolitical factors have further boosted interest, since an open ISA is harder to restrict through export controls than a single vendor's proprietary technology.
Neuromorphic Computing
Neuromorphic computing takes design cues from the brain, using spiking neural networks where information is carried by discrete events (spikes) rather than continuous dense arithmetic. Chips like Intel's Loihi 2 and IBM's TrueNorth and NorthPole colocate memory and computation and process events only when they occur, which can make them extremely energy-efficient for sparse, event-driven workloads. This event-based model suits applications such as always-on sensing, gesture recognition, and certain robotics and optimization problems. The catch is that mainstream deep learning is built around dense tensor math and standard training pipelines, so neuromorphic hardware requires different algorithms and lacks a mature software ecosystem. It remains largely a research and specialized-deployment technology rather than a general-purpose replacement for GPUs.
TPUs and the Case for Custom Silicon
Google's Tensor Processing Unit is the best-known example of a company building its own accelerator rather than buying GPUs. TPUs are built around a large systolic array, a grid of multiply-accumulate units that streams data through in a tightly choreographed pattern to maximize compute per memory access. They are tightly co-designed with the JAX and TensorFlow software stacks and with Google's own optical interconnect, letting TPU pods scale to thousands of chips with high efficiency. Amazon (Trainium and Inferentia), Microsoft (Maia), and Meta (MTIA) have followed with their own in-house accelerators. The strategic logic is control: owning the silicon reduces dependence on a single vendor, tunes hardware to specific models, and can lower total cost at hyperscaler volumes.
Inference Chips Versus Training Chips
Training and inference stress hardware in different ways, and increasingly they use different chips. Training must store activations and gradients for backpropagation, favors high-precision-friendly formats, and benefits enormously from massive clusters with fast interconnects. Inference, by contrast, runs the model forward only, is dominated by latency and cost per token, and rewards high memory bandwidth to stream weights quickly. Startups like Groq, Cerebras, and SambaNova, along with Amazon's Inferentia, target inference specifically, sometimes trading flexibility for dramatically lower latency or better tokens-per-dollar. As deployed AI shifts from research toward serving billions of requests, the economic center of gravity is moving toward inference-optimized silicon.
Chiplets and Advanced Packaging
As it becomes uneconomical to build ever-larger single dies, the industry has shifted to chiplets: smaller dies manufactured separately and then assembled into one package. This improves yield, because defects only ruin a small chiplet rather than a huge monolithic chip, and it lets designers mix process nodes, putting compute on the newest node and I/O on a cheaper mature one. AMD pioneered mainstream chiplet CPUs and applies the approach to its Instinct accelerators, while NVIDIA's Blackwell joins two dies into a single GPU. Standards like UCIe (Universal Chiplet Interconnect Express) aim to make chiplets from different vendors interoperable. Packaging technologies such as TSMC's CoWoS, which also integrates HBM, have themselves become a scarce, throughput-limiting step in the AI supply chain.
Compute in Memory: Key Facts and Data
According to recent industry research and the official documentation linked below:
- The Hopper-based H100 SXM offers 80 GB of HBM3 memory delivering roughly 3.35 TB/s of bandwidth, while the Blackwell B200 pairs two reticle-limited dies into one package with 192 GB of HBM3e and around 8 TB/s of bandwidth.
- NVIDIA has dominated the AI training accelerator market, with industry analysts estimating its share of data-center AI GPUs at well above 80 percent going into 2025, driven largely by the H100 and the newer Blackwell generation.
- Blackwell introduces native support for the FP4 (4-bit floating point) data format, which vendors report can roughly double inference throughput versus FP8 on comparable hardware for suitable models.
Quick-Reference Summary
A map of what this guide covers:
| Topic | What you'll learn |
|---|---|
| Photonic Computing | Photonic computing performs computation using light rather than electrical currents |
| RISC-V in AI Hardware | RISC-V is an open, royalty-free instruction set architecture that has become a popular foundation for custom chips |
| Neuromorphic Computing | Neuromorphic computing takes design cues from the brain |
| TPUs and the Case for Custom Silicon | Google's Tensor Processing Unit is the best-known example of a company building its own accelerator rather than buying GPUs. |
| Inference Chips Versus Training Chips | Training and inference stress hardware in different ways, and increasingly they use different chips. |
| Chiplets and Advanced Packaging | As it becomes uneconomical to build ever-larger single dies |
How to Get Started with Compute in Memory
A simple path that works:
- Learn the fundamentals of Compute in Memory from primary sources, not just tutorials.
- Build one small, real project end to end.
- Get feedback, refactor, and add tests.
- Ship it publicly and document what you learned.
- Repeat with a slightly harder project each time.
Build It with a World-Class Full Stack Developer
Sandeep Kumar Chaudhary is a full stack world-class developer. If you want to turn this into a real, production-ready product, get in touch — message directly on WhatsApp at +9779802348957 for a fast, no-pressure consult.
You can also explore the projects already shipped to thousands of users, or start a conversation here.
Final Thoughts
For on-device and edge AI, look at NPUs in the SoC (Apple, Qualcomm, Intel, AMD) rather than discrete GPUs to hit power and latency budgets. The developers and teams who win in 2026 pair strong fundamentals with consistent shipping. Start small, stay curious, build in public, and revisit this guide as your skills grow.
Sources and Further Reading
Frequently Asked Questions
What Is Compute-in-Memory and How Do Analog MACs Work?
RISC-V is an open, royalty-free instruction set architecture that has become a popular foundation for custom chips, including AI accelerators. Its appeal is extensibility: designers can add custom instructions for tensor or vector operations without licensing fees or permission from a gatekeeper, which is difficult with proprietary ISAs like x86 or Arm. This guide covers compute in memory end to end — core concepts, best practices, concrete data, and a step-by-step approach you can apply right away.
Is RISC-V used in AI hardware?
Yes. RISC-V is an open, royalty-free instruction set that designers can extend with custom instructions, which makes it attractive for building AI accelerators and their control processors. Companies such as Tenstorrent build chips around RISC-V cores, and its vector extension provides a scalable path to data-parallel compute. Its openness also appeals to organizations wary of proprietary-ISA licensing and export restrictions.
What is neuromorphic computing good for?
Neuromorphic chips like Intel's Loihi 2 use spiking neural networks that process discrete events only when they occur, making them very energy-efficient for sparse, event-driven workloads. They suit applications such as always-on sensing, gesture recognition, and certain robotics and optimization tasks. However, mainstream deep learning relies on dense tensor math and mature training pipelines, so neuromorphic hardware remains largely research-stage rather than a general GPU replacement.
Should my team buy AI chips or rent them in the cloud?
For most teams, renting cloud capacity is the pragmatic choice because it turns a large capital purchase into an elastic operating cost and provides access to the newest accelerators without hardware lead times. Buying can make sense at very large, steady-state scale where owning hardware lowers long-run cost and you can keep it highly utilized. Either way, benchmark on a representative slice of your own workload and account for total cost of ownership including power, cooling, and software effort.
What are chiplets and why is the industry moving to them?
Chiplets are smaller dies made separately and assembled into a single package instead of building one large monolithic chip. They improve manufacturing yield, since a defect only ruins a small chiplet, and let designers mix process nodes to optimize cost. Modern high-end accelerators like NVIDIA's Blackwell and AMD's Instinct use this approach, and standards such as UCIe aim to let chiplets from different vendors work together.
Sandeep Kumar Chaudhary
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